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(通译)FIFO In Hardware

优良自学吧提供(通译)FIFO In Hardware,(翻译)FIFO In Hardware翻译一些自己觉得有价值的材料,工作中碰到英语大多数是读,基本没有写或者翻的,翻得不好不到位的敬请指摘。 同时也附原文以供参考。 http://electronics.stackexchange.com/questions/9728

(翻译)FIFO In Hardware

翻译一些自己觉得有价值的材料,工作中碰到英语大多数是读,基本没有写或者翻的,翻得不好不到位的敬请指摘。

同时也附原文以供参考。

http://electronics.stackexchange.com/questions/97280/trying-to-understand-fifo-in-hardware-context

 

翻译:

Wiki定义FIFO in electronics如下:

  FIFO常被用于电路缓冲及计算机软硬件的流量控制。在硬件方面,FIFO主要包含一组读写指针,存储器和控制逻辑。

FIFO,先进先出,数据从一端塞进去,从另一端取出来。可存储的数据量有一个上限。

然而,在硬件的内存地址中实际移动数据代价高昂。比较好的方式是,通过控制接下来要读和写的地址,使得使用这些内存地址如同在一段循环的缓冲队列一样。这些地址分布在寄存器中,常被成为读指针和写指针。

下图是一份8个地址FIFO的简要说明:

(通译)FIFO In Hardware

下个接受的字将被写在地址1(写指针所指向的位置),然后写指针+1指向地址2。下一个读请求取出地址5里的值(读指针所指向的位置),然后读指针+1指向地址6。在这个例子中,这些地址是环状的,地址7再加1会回到地址0。

完善的FIFO系统需要检测空状态和满状态。对此有不同的实现方式。一个单独的寄存器可以用来记录此FIFO中有多少个word,上图中为4个。(这种方式你会使用一个额外的word或预留一个不用的word,可能还需要知道总量?

另一个有用的方式是比较读指针和写指针。例如,两个指针相等则FIFO为空状态,写指针比读指针小1则为满状态,注意这种实现方式为留下一个不会被使用的word。(这种方式你会浪费一个word,想想其实跟第一种方法差不多

这样能够避免读写冲突,不用在读写间加互斥锁。

原文:

Wikipedia defines the FIFO in electronics as under:

  FIFOs are commonly used in electronic circuits for buffering and flow control which is from hardware to software. In its hardware form, a FIFO primarily consists of a set of read and write pointers, storage and control logic.

A FIFO is a First In First Out memory. You can think of data being shifted in one end and shifted out the other, with the amount of data in the FIFO being allowed to grow up to some maximum limit.

However, actually shifting data around in memory is costly to do in hardware. A better way is to use a memory more normally but make it look like a circular buffer by manipulation of the next address to write to and read from. These addresses live in separate registers, and are often called the read pointer and the write pointer.

Here is a illustration of the state for a simple FIFO using a 8-word memory:

(通译)FIFO In Hardware

The next incoming word will be written to the empty word at address 1 (the value of the write pointer), then the write pointer incremented to 2. The next read request will fetch the word at 5 (the value of the read pointer), then the read pointer is incremented by 1. In this example, the addresses are automatically circular if the pointers are 3 bits wide. Adding 1 to 7 yields 0 in 3-bit unsigned math.

Complete FIFO systems need ways to indentify the full and empty conditions. There are various schemes for this. A separate register could be used to keep track of how many words are in the FIFO, which is 4 in the snapshot shown above.

A useful scheme for a firmware implementation is to compare the read and write pointers. You could, for example, decide that both pointers equal is FIFO empty, and write one behind read (after wrapping) is FIFO full. Note that such schemes will leave one word of the FIFO unused. You end up spending a piece of state somewhere to allow detection of full and empty, whether that's a separate register or a unusable word in the FIFO. The advantage of this scheme is that reads and writes can happen independently without conflict, so such a FIFO doesn't need a mutex between reading and writing. For example, you don't have to disable interrupts when reading because no harm is done if a interrupt routine pushes a word onto the FIFO while foreground code is trying to read.


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